The present invention relates generally to phase control for signal processors and more particularly to a method and system for color television signal synchronization to provide the appropriate phase relation to a reference.
In signal processors, particularly those found in television video recorders of the type used in television studios, the phasing of the various time reference signals generated by the processor sync generator is extremely important if undesirable sync-related disturbances are to be avoided. The TV signal processor may be "genlocked" to an external reference video signal, thus permitting phase adjustment of locally generated reference signals such as subcarrier and horizontal sync.
As the phasing of one or more reference signals is adjusted, relative phase ambiguities can occur. Such ambiguities can cause unacceptably large disturbances in picture reproduction or complete loss of sync lock.
It is therefore an object of the present invention to provide a novel method and system for detecting a region of potential phase ambiguity between two reference signals in a signal processor, particularly for television signals, and eliminating the ambiguity without unacceptable disturbances or loss of data.
It is another object of the present invention to provide a novel method and system for composite phase control of the reference signals in a video signal processor whereby phase adjustment of one signal does not cause unacceptable disturbances or loss of data due to passage through a region of ambiguous relative phase.
It is a more specific object of the present invention to provide a novel color television processor synchronizing system and method for providing subcarrier phase control through a range exceeding one subcarrier cycle without undesirable phase hops in a locally generated (horizontal) reset signal due to coincidence ambiguity as subcarrier phase is adjusted.
It is yet another object of the present invention to provide a novel color television signal processor synchronizing system and method for providing a composite system phase control such that the phase of the reconstituted subcarrier can be adjusted by a single control through more than one subcarrier cycle without undesirable disturbances.
In accordance with the present invention, a plurality of timing reference signals are produced from a composite data signal such as a television signal. A predetermined condition of time coincidence between two of the reference signals (e.g. the occurrence of a particular edge or transition of one signal, used as a clock, during a particular logic level of another signal) produces a synchronizing signal, preferably a video frame-rate horizontal reset pulse which phases the horizontal-rate pulses in the processor sync generator. An ambiguity detector determines when a condition of potential coincidence ambiguity exists, i.e. when the phase relationship between the two reference signals is such that the point of time coincidence and thus the timing of the generated synchronizing signal may vary irregularly by a significant amount for slight variance in the relative phase relationship of the two reference signals. When such an ambiguity condition is detected, the phase of one of the reference signals is shifted 180 degrees, to eliminate the coincidence ambiguity. In the preferred embodiment that reference signal is a clock signal designated F.sub.sc and has a frequency of the color subcarrier signal. Simultaneously, the phase of the generated synchronizing signal is shifted by at least one-half cycle of the F.sub.sc clock signal.
Since the ambiguity detector can either advance or retard the timing of the generated synchronizing signal by one-half cycle of the one reference signal, the F.sub.sc clock, there are two possible conditions when the the F.sub.sc clock is inverted to eliminate the coincidence ambiguity. Firstly, the shift in the generated synchronizing signal resulting from the one-half cycle phase shift in the F.sub.sc clock can be compensated by a one-half cycle phase shift of the generated synchronizing signal in the direction which shifts it back to its original position. Secondly, the generated synchronizing signal can be shifted one-half cycle in the opposite direction resulting overall in a one F.sub.sc cycle phase shift of the generated synchronizing signal from its original position. While the first one-half cycle transition is transparent, the second is not unless the one F.sub.sc cycle shift is compensated.
In accordance with the preferred embodiment of the present invention, the system controller, which controls both system subcarrier phase and horizontal phase, monitors the condition of the ambiguity detector output. Thus, if the second condition exists and the generated synchronizing signal shifts by one cycle of F.sub.sc, the system controller detects the change in the ambiguity control signal and, by knowing the direction of system subcarrier phase change, either increments or decrements the horizontal phase data to compensate the one cycle phase shift. Because the generated synchronizing signal occurs at a frame rate, there is ample time for the system controller to send the new horizontal phase data between the time that an ambiguity change is detected and the following generated synchronizing signal.